Author: (\/)@{-}!
•10:31 AM
An interface encapsulate a group of inter-related wires, along with their directions (via mod-ports) , synchronization details (via clocking block) , functions and tasks. The major usage of interface is to simplify the connection between modules. 

But Interface can't be instantiated inside program block, class (or similar non-module entity in System Verilog). But we needed to be driven from verification environment like class. To solve this issue virtual interface concept was introduced in System Verilog.

A virtual interface is just a pointer to a physical interface. i.e. Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface). It provides a mechanism for separating abstract models and test programs from the actual signals that make up the design. Another big advantage of virtual interface is that class can dynamically connect to different physical interfaces in run time.
Example :
                       
             interface  ahb_vip_intf ; 
                  
 ................ ;

                   ................ ;             
            endinterface 

         

            class AHB_driver ;
                virtual ahb_vip_intf  intf;
                functional new(input virtual ahb_vip_intf intf);
                        this.intf = intf;
                endfunction
              
               task main() ;
                   intf.sig1 =1;
                   ........ ;
               endtask
          endclass
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